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IPRC (ISRO) Technical Assistant (Electronics): Previous Paper 2018 (Held On: 21 April 2018)

Option 1 : 15 ns

ST 1: Basic Electrical Engineering

3701

20 Questions
20 Marks
20 Mins

__Concept__:

The maximum propagation delay (t_{pd}) for the synchronous counter is given by:

t_{pd} = t_{d}

t_{d} = Propagation delay of 1 Flip flop.

__Calculation__:

Given is a 4-bit synchronous counter for which the maximum possible time needed for the change of state will be the maximum possible propagation delay:

t_{pd} = Delay of 1 flip-flop only

t_{pd} = 15 ns

- In synchronous counters, all flip-flops change simultaneously and in asynchronous counters, the propagation delay of the flip-flops add up to produce the overall delay.
- Although synchronous counters usually have more combinational logic, the propagation delay through these gates is small compared to the propagation delay through many stages of flip-flops.
- So the Synchronous counter will provide the least delay compared to Asynchronous counters.

The maximum propagation delay for an n-bit asynchronous counter is given by:

t_{pd} = n × t_{d}